The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).
The CMOS SRAM, in which are combined a high resistance load type or complete CMOS (Complementary Metal-Oxide-Semiconductor) type memory cell and a peripheral circuit composed of a complementary MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor) (CMOSFET), has been used for a cache memory of a computer or workstation of the prior art
The memory cell of the CMOS SRAM is composed of a flip-flop circuit for storing information of 1 bit, and two transfer MISFETs. The flip-flop circuit of the high resistance load type is composed of a pair of driver MISFETs and a pair of resistance elements, whereas the flip-flop circuit of the complete CMOS type is composed of a pair of driver MISFETs and a pair of load MISFETs.
In recent years, the SRAM of this kind has been required to miniaturize the memory cell size to increase the capacity and speed and to lower the operating voltage to reduce the power consumption of the system. However, to meet the requirement, a problem that the resistance to soft error due to alpha rays (d-ray) must be solved.
The soft error due to alpha rays is a phenomenon that alpha rays (He nuclei) contained in cosmic rays or emitted from radioactive atoms contained in the resin materials of LSI packages, come into the memory cell to break the information retained in the information storage section.
An alpha particle has an energy of 5 eV and produces an electron-hole pair when it is incident upon the silicon (Si) substrate. When an alpha ray comes into a storage node at a xe2x80x9cHighxe2x80x9d potential level, of the memory cell, the electron produced by the alpha-ray, flows to the storage nodes so that the hole flows to the substrate. As a result, the charge and potential of the storage node instantly decrease to invert the information of the memory cell with a certain probability.
In the case of an SRAM, the increase in the storage node capacitance of the memory cell is effective in improving the aforementioned resistance to soft error due to alpha rays.
U.S. Pat. No. 5,483,083 discloses a TFT (Thin Film Transistor) complete CMOS SRAM in which the load MISFETs are made of two-layered polycrystalline silicon film formed over the driver MISFET. In the SRAM, as disclosed, the gate electrode of one of the load MISFETs is partially extended to above the source or drain region of the other of the load MISFETs, and a capacitor element is formed of the gate electrode, the source or drain region and a insulating film interposed between the former two so that the storage node capacitance may be increased.
Thus, in the high resistance load SRAM and the TFT complete CMOS SRAM, countermeasures have been taken in the prior art to increase the storage node capacitance of the memory cell.
It has been considered that in the case of the so-called bulk CMOS SRVI, out of the complete CMOS SRAM, in which all the six MISFETs consisting a memory cell are formed in the semiconductor substrate, any countermeasure to increase the storage node capacitance is unnecessary.
The reason will be described in the following. A bulk CMOS SRAM having load MISFETs formed in a semiconductor substrate has a high current driving ability and a large storage node capacitance because the area of the load MISFETs is relatively large. As a result, sufficient charge can be fed to the storage node even if the potential of the storage node is fluctuated by the incidence of a alpha ray.
However, we have found out the following fact. In the bulk CMOS SRAM, too, the current driving ability of the load MISFETs drops if the miniaturization of the memory cell size further advances. If the operation voltage further drops, the amount of charge stored in the storage node drops, so that the potential fluctuation of the storage node due to alpha rays cannot be suppressed, deteriorating the soft error resistance.
An object of the present invention is to provide a technique capable of improving the soft error resistance of an SRAM adopting the bulk CMOS type.
Another object of the present invention is to provide a technique capable of promoting the miniaturization of the SRAM adopting the bulk CMOS type.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The representatives of the invention to be disclosed herein will be summarized in the following.
According to the semiconductor integrated circuit device of the present invention, in a complete CMOS SRAM in which the gate electrodes of a pair of driver MISFETs, a pair of load MISFETs and a pair of transfer MISFETs constituting a memory cell are composed of a first conductive film formed over the principal face of a semiconductor substrate, a capacitor element is composed of a second conductive film formed over the memory cell, an insulating film (dielectric film) formed over the second conductive film, and a third conductive film formed over the insulating film, the second conductive film and one of the storage nodes of the memory cell are electrically mutually connected, and the third conductive film and the other storage node of the memory cell are electrically connected.
In the semiconductor integrated circuit device, the one electrode of the capacitor element and the one storage node are electrically connected to each other through one of a pair of metal wiring lines composed of a first metal film formed over the third conductive film, and the other electrode of the capacitor element and the other storage node are electrically connected to each other through the other of the paired metal wiring lines.
In the semiconductor integrated circuit device of the present invention: the second conductive film constituting the one electrode of the capacitor element and the third conductive film constituting the other electrode of the capacitor element are individually composed of n-type polycrystalline silicon films; the one electrode of the capacitor element is electrically connected to the drain region of one of the paired driver MISFETs through a first contact hole and to one of the paired metal wiring lines through a second contact hole made above the first contact hole; and the other electrode of the capacitor element is electrically connected to the drain region of the other of the paired driver MISFETs through a third contact hole and to the other of the paired metal wiring lines through a fourth contact hole made above the third contact hole.
In the semiconductor integrated circuit device of the present invention: the second conductive film constituting the one electrode of the capacitor element and the third conductive film constituting the other electrode of the capacitor element are individually composed of n-type polycrystalline silicon films; the one electrode of the capacitor element is electrically connected to the one metal wiring line at the side wall of a fifth contact hole for connecting one of the paired metal wiring lines to the drain region of one of the paired driver MISFETs electrically; and the other electrode of the capacitor element is electrically connected to the other metal wiring line at the side wall of a sixth contact hole for connecting the other of the paired metal wiring lines and the drain region of the other of the paired driver MISFETs electrically.
In the semiconductor integrated circuit device of the present invention: the second conductive film constituting the one electrode of the capacitor element and the third conductive film constituting the other electrode of the capacitor element are composed of an n-type polycrystalline silicon film and a p-type polycrystalline silicon film respectively; the one electrode composed of the n-type polycrystalline silicon film is electrically connected to the drain region of the one of the paired driver MISFETs through a seventh contact hole and to the one of the paired metal wiring lines through an eighth contact hole made above the seventh contact hole; and the other electrode composed of the p-type polycrystalline silicon film is electrically connected to the drain region of the other of the paired load MISFETs through a ninth contact hole-and to the other of the paired metal wiring lines through a tenth contact hole made above the ninth contact hole.
In the semiconductor integrated circuit device of the present invention, a reference voltage line for feeding a reference voltage to the source regions of the paired driver MISFETs and a power voltage line for feeding a power voltage to the source regions of the paired load MISFETs are composed of the first metal film.
In the semiconductor integrated circuit device of the present invention: a pair of complementary data lines are composed of a second metal film formed over the first metal film; one of the paired complementary data lines is electrically connected to the source region of one of the paired transfer MISFETs through one of a pair of pad layers composed of the first metal film; and the other of the paired complementary data lines is electrically connected to the source region of the other of the paired transfer MISFETs through the other of the paired pad layers.
In the semiconductor integrated circuit device of the present invention, the capacitor element having the second conductive film, an insulating film formed over the second conductive film and a third conductive film formed over the insulating film is formed in the peripheral circuit of the SRAM.
In the semiconductor integrated circuit device of the present invention, the MISFETs constituting the peripheral circuit of the SRAM and the metal wiring lines formed over the third conductive film are electrically connected through the pad layers composed of the second conductive film or the third conductive film.
A process for manufacturing a semiconductor integrated circuit device of the present invention, comprises:
(a) the step of forming the gate electrodes of the driver MISFETs, the load MISFETs and the transfer MISFETs, of a first conductive film over the principal face of a semiconductor substrate;
(b) the step of forming a pair of electrodes and a capacitor insulating film (dielectric film) of a capacitor element, of a second conductive film over the first conductive film, an insulating film over the second conductive film, and a third conductive film over the insulating film; and
(c) the step of forming a pair of metal wiring lines by patterning a first metal film, formed over the third conductive film, to connect one electrode of the capacitor element and one storage node of the memory cell electrically through one of the paired metal wiring lines and to connect the other electrode of the capacitor element and the other storage node of the memory cell electrically through the other of the paired metal wiring lines.
A semiconductor integrated circuit device manufacturing process of the present invention, comprises:
(a) the step of forming the paired driver MISFETs, the paired load MISFETs and the paired transfer MISFETs, and then making a first contact hole reaching the drain region of one of the paired driver MISFETs by etching a first insulating film formed over these MISFETS;
(b) the step of forming one electrode of the capacitor element by patterning the second conductive film of an n-type polycrystalline silicon film, formed over the first dielectric film, to connect one electrode of the capacitor element and the drain region of the one of the driver MISFETs electrically through the first contact hole;
(c) the step of forming the capacitor insulating film (dielectric film) over the one electrode of the capacitor element, and then making a second contact hole reaching the drain region of the other of the paired driver MISFETs and the gate electrode common to the one of the driver MISFETs and one of the paired load MISFETs by etching the capacitor insulating film;
(d) the step of forming the other electrode of the capacitor element by patterning the third conductive film of an n-type polycrystalline silicon film, formed over the capacitor element, to mutually connect the other electrode of the capacitor element, the drain region of the other of the driver MISFETS, and the gate electrode common to the one of the driver MISFETs and the one of the load MISFETs, electrically through the second contact hole;
(e) the step of making a third contact hole reaching the one electrode of the capacitor element, a fourth contact hole reaching the other electrode of the capacitor element, a fifth contact hole reaching the drain region of the one of the driver MISFETs and the gate electrode common to the other of the paired load MISFETs and the other of the driver MISFETs, and a sixth contact hole reaching the drain region of the other of the load MISFETs; and
(f) the step of forming, by patterning the first metal film formed over the interlayer insulating film: a first metal wiring line, one end of which is electrically connected through the third contact hole to one electrode of the capacitor element and the other end of which is electrically connected through the fifth contact hole to the drain region of the one of the driver MISFETs and the gate electrode common to the other of the load MISFETs and the other of the driver MISFETs; and a second metal wiring line, one end of which is electrically connected through the fourth contact hole to the other electrode of the capacitor element and the other end of which is electrically connected through the sixth contact hole to the drain region of the other of the load MISFETs.
A semiconductor integrated circuit device manufacturing process of the present invention comprises:
(a) the step of making a seventh contact hole reaching the source region of one of the paired transfer MISFETs and an eighth contact hole reaching the source region of the other of the paired transfer MISFETs;
(b) the step of forming a first pad layer electrically connected to the source region of the one of the transfer MISFETs through the seventh contact hole, and a second pad layer electrically connected to the source region of the other of the transfer MISFETs through the eighth contact hole, by patterning the first metal film;
(c) the step of making a ninth contact hole reaching the first pad layer and a tenth contact hole reaching the second pad layer, by etching a second interlayer insulating film formed over the first metal film; and
(d) the step of forming one of complementary data lines electrically connected to the first pad layer through the ninth contact hole and the other of the complementary data lines electrically connected to the second pad layer through the tenth contact hole, by etching a second metal film formed over the second interlayer insulating film.
A semiconductor integrated circuit device manufacturing process of the present invention comprises:
(a) the step of forming, after all of the paired driver MISFETs, the paired load MISFETs and the paired transfer MISFETs have been formed, a first insulating film over all of the MISFETs and then forming one electrode of the capacitor element by patterning the second conductive film of an n-type polycrystalline silicon film, formed over the first insulating film;
(b) the step of forming the other electrode of the capacitor element, after the capacitor insulating film has been formed over the one electrode of the capacitor element, by patterning the third conductive film of an n-type polycrystalline silicon film formed over the insulating film;
(c) the step of making, by etching the first interlayer insulating film formed over the other electrode of the capacitor element: a first contact hole reaching the drain region of one of the paired driver MISFETs through one electrode of the capacitor element; a second contact hole reaching the drain region of one of the paired load MISFETs and the gate electrode connected the other of the paired load MISFETs and the other of the paired driver MISFETs; a third contact hole reaching the drain region of the other of the driver MISFETs and the gate electrode common to the one of the driver MISFETs and the one of the load MISFETs through the other electrode of the capacitor element; and a fourth contact hole reaching the drain region of the other of the load MISFETs; and
(d) the step of forming, by patterning the first metal film formed over the interlayer insulating film: a first metal wiring line, one end of which is electrically connected through the first contact hole to one electrode of the capacitor element and the drain region of the one of the driver MISFETs, and the other end of which is electrically connected through the second contact hole to the drain region of the one of the load MISFETs and the gate electrode common to the other of the load MISFETs and the other of the driver MISFETs; and a second metal wiring line, one end of which is electrically connected through the third contact hole to the other electrode of the capacitor element, the drain region of the other of the driver MISFETs and the gate electrode common to the one of the load MISFETs and the one of the driver MISFETs, and the other end of which is electrically connected through the fourth contact hole to the drain region of the other of the load MISFETs.
A semiconductor integrated circuit device manufacturing process of the present invention comprises:
(a) the step of forming the paired driver MISFETs, the paired load MISFETs and paired transfer MISFETs, and then making a first contact hole reaching the drain region of the other of the paired load MISFETs by etching the first insulating film formed over all of the MISFETs;
(b) the step of forming one electrode of the capacitor element by patterning the second conductive film composed of a p-type polycrystalline silicon film formed over the first insulating film to connect one electrode of the capacitor element and the drain region of the other of the load MISFETs electrically through the first contact hole;
(c) the step of forming the insulating film over the one electrode of the capacitor element, and making a second contact hole reaching the drain region of the one of the paired driver MISFETs, by etching the insulating film;
(d) the step of forming the other electrode of the capacitor element by patterning the third conductive film of an n-type polycrystalline silicon film formed over the insulating film to connect the other electrode of the capacitor element and the drain region of the one of the driver MISFETs electrically through the second contact hole;
(e) the step of making, by etching the first interlayer insulating film formed over the other electrode of the capacitor element: a third contact hole reaching the one electrode of the capacitor element; a fourth contact hole reaching the other electrode of the capacitor element; a fifth contact hole reaching the drain region of the one of the driver MISFETs and the gate electrode common to the other of the load MISFETs and the other of the paired driver MISFETs; and a sixth contact hole reaching the drain region of the other of the driver MISFETS, the one of the paired load MISFETs and the one of the driver MISFETS; and
(f) the step of forming, by patterning the first metal film formed over the interlayer insulating film: a first metal wiring line one end of which is electrically connected through the fourth contact hole to the other electrode of the capacitor element and the other end of which is electrically connected through the sixth contact hole to the drain region of the one of the load MISFETs and the gate electrode common to the other of the load MISFETs and the other of the driver MISFETs; and a second metal wiring line one end of which is electrically connected through the third contact hole to the one electrode of the capacitor element and the other end of which is electrically connected through the sixth contact hole to the drain region of the other of the driver MISFETs and the gate electrode common to the one of the load MISFETs and the one of the driver MISFETs.
A semiconductor integrated circuit device manufacturing process of the present invention comprises: the step of thinning, prior to the step of making contact holes reaching both the gate electrode common to the one of the paired driver MISFETs and the one of the paired load MISFETs and the gate electrode common to the other of the paired driver MISFETs and the other of the paired load MISFETs by etching the first interlayer insulating film, a portion of the insulating film covering the individual ones of the gate electrodes.
According to the means described above, one of the electrodes of the capacitor element composed of the second conductive film, the third conductive film and the insulating film interposed between the two conductive films, is connected to one storage node, and the other electrode is connected to the other storage node, so that sufficient charge is fed to the storage nodes through the capacitor element. As a result, even when the memory cell is miniaturized or when the operating voltage is lowered, the potential fluctuation of the storage nodes due to alpha rays is suppressed to improve the soft error resistance of the memory cell.
By constructing a capacitor element of the peripheral circuit using the two-layered conductive film deposited on the semiconductor substrate, according to the means described above, the area occupied by the elements can be made smaller than that of the capacitor element using a diffused layer (pn junction) formed over the semiconductor substrate, so that the area of the peripheral circuit can be reduced to raise the degree of integration of the SRAM.
By connecting the semiconductor regions of the MISFETs and the wiring lines through the pad layers which are formed at the same step as that of the electrodes of the capacitor element, according to the means described above, the mask aligning margin at the time when the connection is made over the semi-conductor region by etching using a photoresist as the mask can be reduced to reduce the area of the MISFETs and thereby to raise the degree of integration of the SRAM.
By thinning a portion of the insulating film covering the gate electrodes prior to the step of making contact holes reaching the gate electrodes, according to the means described above, the gate electrodes can be exposed by etching in a short time, so that the remaining regions can be prevented from being over-etched to prevent the erosion of the field dielectric film.